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Tensilica Delivers New Design Flow Support for Synopsys’ Galaxy Implementation Platform Technologies

16th December 2009

Tensilica

ES Admin

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Tensilica, Inc. today announced that it now provides out-of-the-box automated design flow support for key technologies within Synopsys' Galaxy Implementation Platform, including DC Ultra RTL synthesis and IC Compiler place-and-route, for Tensilica's new Xtensa 8 and Xtensa LX3 dataplane processors (DPUs). This latest design flow provides up to 15% improvement in processor speed, area and power, in addition to faster design closure over previous Synopsys-based design flows, thus offering immediate benefits to Tensilica customers.

Tensilica delivers scripting support to help customers exploit advanced technologies provided by Synopsys' Galaxy platform, including Topographical technology, congestion driven placement, pin placement optimization, useful skew, and Zroute, which collectively provide high frequency with area-efficient layout.

Tensilica's DPU IP cores are increasingly used in a variety of power-and-performance critical dataplane and signal processing applications, stated Steve Smith, senior director, platform marketing at Synopsys. Galaxy's advanced synthesis, optimization and place-and-route technologies deliver a more efficient implementation for Tensilica-based designs.

Synopsys has delivered on what it promised with DC Ultra and IC Compiler, stated Ashish Dixit, Tensilica's vice president of hardware engineering. We have seen consistently better quality of results with these tools and anticipate that our customers will take full advantage of the support we provide.