Synopsys' VIP supports Micron's Hybrid Memory Cube architecture
Synopsys has announced its next-gen VIP (Verification IP) for Micron's Hybrid Memory Cube (HMC) architecture. The HMC architecture offers a high performance, low cost memory solution, with 70% less energy utilisation than existing DRAM technologies. Synopsys VC VIP for HMC enables the design of next-generation high-speed memory technologies with ease of use, fast integration and optimum performance, resulting in accelerated verification closure.
Synopsys VC VIP for HMC uses a next-gen native SystemVerilog Universal Verification Methodology (UVM) architecture that enables ease of integration within existing verification environments to accelerate time to first test. VC VIP for HMC is integrated with Synopsys' Verdi Protocol Analyzer's memory-aware graphical debug solution and features advanced debug ports for easy and fast debug. Built-in coverage and verification plans are also included to speed up verification coverage closure.
Vikas Gautam, Group Director, VIP R&D and corporate applications, Verification Group, Synopsys, commented: "We continue to collaborate extensively with leading-edge companies as the latest protocols are developed, to deliver increased performance and features. With the introduction of Synopsys HMC VIP to support Micron's HMC products, we provide SoC teams with access to the latest specifications and capabilities for accelerated verification closure of next-generation high speed memory designs."
VC VIP for HMC is available now as a standalone product and as part of the Synopsys VIP Library.
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