Synopsys speeds timing signoff by 2X with latest multicore technology

“At Synopsys we recognise that IC designers are being asked to develop bigger, more complex chips on the same schedules as previous generations, putting more pressure on timing signoff turnaround time,” said Ahsan Bootehsaz, vice president of engineering for design analysis and signoff at Synopsys. “IC designers are working with diverse compute environments that are comprised of multiple classes of multicore compute servers. PrimeTime 2009.12 completes our vision of delivering a comprehensive solution that enables a broad set of designers to take full advantage of multicore performance.”

“The threaded multicore capabilities in PrimeTime 2009.12 reduced our runtime on a 48 million gate design by over 40%, significantly reducing our signoff time-to-results,” said Michael Trocino, IC Design Manager at Coherent Logix. “It gives us the flexibility with PrimeTime’s distributed multicore capability to utilise our existing compute resources more efficiently and to take advantage of new hardware as our farm grows.”

Synopsys’ gold standard PrimeTime static timing and signal integrity (SI) analysis tool, a key signoff component of the Galaxy(tm) Implementation Platform, includes three key technologies that collectively make it one of the most flexible and comprehensive multicore static timing solutions today. First, PrimeTime’s threaded multicore capability boosts runtime efficiency on a multicore compute server, delivering up to a 2X speed up utilising just four cores. Second, PrimeTime’ distributed multicore capability can divide very large designs across a compute farm enabling the use of more readily available smaller compute servers. Synopsys’ engineers have solved the challenge of handling the large highly-coupled parasitic netlists used in SI analysis with minimum overhead and partition-to-partition communication while maintaining golden accuracy and runtime performance. And third, PrimeTime pioneered distributed multi-scenario analysis (DMSA), which allows designers to perform timing analysis and ECO fixing simultaneously across multiple scenarios on multiple compute servers, thereby significantly reducing design iterations and overall turnaround time.