Synopsys first to announce DDR3 IP with support for 2133 Mbps data rates and 1.35V DDR3L

The DesignWare DDR3/2 IP targets an extensive range of high performance applications such as digital home, digital office, data centre and storage that all require bandwidth in excess of 1066 Mbps per pin. To support the full range of DDR3 data rates, the DesignWare DDR3/2 IP includes a unique PHY Utility Block with built-in data training circuits to enable in-system calibration, providing optimised system-level timing. As part of the data training sequence, the DDR3/2 IP includes the ability to remove bit-to-bit timing skew that can occur on the chip, in the package or on the circuit board. Removing the timing skew is necessary to achieve reliable system-level performance at data rates above 1066Mbps.

The DesignWare DDR3/2 PHY provides designers with a choice of interfaces to the memory controller IP. For the lowest latency interface, designers can utilise the complementary DesignWare DDR3/2 Memory Controller or Protocol Controller IP. Support for internally developed controllers is offered via an optional DFI2.1 compliant interface on the DDR3/2 PHY that provides designers with a common interface to ease the integration effort between the controller and PHY.

“High speed DDR interfaces represent a unique challenge for today’s SoC designs,” said Jim Finnegan, senior vice president of silicon engineering at Netronome Systems. “The high quality DesignWare DDR3/2 PHY and controller IP allowed us to achieve our design objectives and Synopsys provided Netronome with access to a team of DDR experts that was invaluable as we pushed towards the completion of our latest chip design.”

“DDR3 SDRAMs are rapidly evolving to offer both higher performance and lower power consumption,” said John Koeter, vice president of marketing for the Solutions Group at Synopsys. “By providing early access to enhancements in the JEDEC standard DRAM roadmap, Synopsys is enabling designers to take full advantage of the latest advances in DDR technology. With a proven track record of over 200 DRAM interface design wins with more than 150 companies, Synopsys offers a low-risk path to working silicon.”

The DesignWare DDR3/2 IP is a part of Synopsys’ complete DesignWare DDR IP offering that consists of digital controllers, PHY and verification IP supporting DDR2, DDR3 and Mobile DDR. The comprehensive portfolio of DDR IP supports leading 130nm, 90nm, 65nm, 55nm and 45/40nm technologies. Synopsys helps lower integration risk by providing DDR IP solutions that have been implemented in hundreds of applications and are shipping in high-volume production.