/> Because of the tight form factor of our package, only three scan input-output pairs were available for testing our design, said Narasimha Nookala, senior director IC engineering at Silicon Image. DFTMAX compression for pin-limited test reduced test time and data by more than 95 percent while maintaining high defect coverage, making it a key component in the rigorous testing process we employ to deliver high quality products.

The demand for more functionality, smaller area and lower cost is leading to more stringent IC packaging constraints that limit the number of pins that can be allocated for test. In addition, to manage the complexity of large systems-on-chip, designers are deploying core-based methodologies that restrict access of embedded test compression logic to only a few chip-level pins. Multi-site testing, a technique that targets multiple die simultaneously to reduce test time, is also stimulating the demand for pin-limited test because each die has access to fewer tester channels.

Synopsys recently extended DFTMAX compression to enable predictable high compression for designs and methodologies that mandate as few as one pair of test data pins. Built into the Galaxy Implementation Platform to eliminate time-consuming iterations between synthesis, scan insertion and physical implementation, Synopsys' DFTMAX compression and TetraMAX(r) ATPG provide designers a comprehensive solution for meeting their most challenging quality and cost goals for test.

Increased focus on packaging size and cost is driving the need to utilise fewer pins for manufacturing test, said Bijan Kiani, vice president of product marketing at Synopsys. Silicon Image and other Synopsys customers are now benefiting from the superior quality of results attainable using DFTMAX compression to lower the cost of pin-limited testing.