Synopsys Announces Immediate Availability of DesignWare MIPI M-PHY IP in 40-nm Process Technology

The configurable MIPI DigRF V4 Master Controller and M-PHY hard macro are compliant to the MIPI Alliance specifications. Utilizing a single-vendor solution enables designers to lower the risk and cost of integrating these MIPI interfaces into baseband and application processor integrated circuits (ICs), speeding time-to-market of advanced semiconductor solutions for LTE and Mobile WiMAX.

The DesignWare MIPI M-PHY implements all required physical layer functionality defined in the MIPI DigRF v4 specification. The DesignWare MIPI M-PHY is designed to meet the stringent power consumption guidelines of the MIPI M-PHY specification, keeping the energy expenditure below 15pJ/bit for typical LTE applications. The integrated analog Phase Lock Loop (PLL) and biasing block are designed to help guarantee the integrity of the high-speed clocks and signals required to meet the strict timing requirements of the protocol, affording designers a robust and low risk solution. In addition, the DesignWare MIPI M-PHY supports the optional dithering functionality defined in the MIPI DigRF v4 specification to further lower Electromagnetic Interference (EMI).

As an active contributor to the MIPI working groups, Synopsys continues to make solid contributions that support the MIPI Alliance portfolio of specifications, said Joel Huloux, chairman of the MIPI Alliance. Synopsys is speeding the adoption of the new M-PHY interface into mobile devices and helping designers benefit from the latest functionality offered by the MIPI-based technology.

To address the growing usage of multimedia content in mobile devices, designers are using standards-based interfaces from the MIPI Alliance to help them meet the increased data throughput requirements for mobile terminals targeting 4G standard air interfaces, said John Koeter, vice president of marketing for the Solutions Group at Synopsys. Synopsys is playing a key role in supporting the MIPI ecosystem by providing designers with high-quality DesignWare MIPI IP consisting of DigRF v3/v4, CSI-2, D-PHY, and M-PHY IP, enabling them to lower the risk of integrating MIPI interfaces into their designs.