Synopsys' Design Compiler 2010 doubles productivity of synthesis and place and route

A new capability allows RTL designers to perform floorplan exploration within the synthesis environment to efficiently achieve an optimal floorplan. Additionally, Design Compiler’s new scalable infrastructure tuned for multicore processors yields 2X faster synthesis runtimes on four cores. These new Design Compiler 2010 productivity improvements will be highlighted today by users at the Synopsys Users Group (SNUG) meeting in San Jose, California.



“Cutting design time and improving design performance are essential to keep our competitiveness in the marketplace,” said Hitoshi Sugihara, department manager, DFM & Digital EDA Technology Development at Renesas Technology Corp. “With the new physical guidance extension to topographical technology we are seeing 5 percent correlation between Design Compiler and IC Compiler, up to 2X faster placement in IC Compiler and better design timing. We are adopting the new technology innovations in Design Compiler to minimise iterations while meeting our design goals in shorter timeframes.”



To alleviate today’s immense time-to-market pressures, Design Compiler 2010 extends topographical technology to further optimise its links with IC Compiler, tightening correlation down to 5 percent. Additional physical optimisation techniques are applied during synthesis, and physical guidance is created and passed to IC Compiler, streamlining the flow and speeding up placement in IC Compiler by 1.5X. Design Compiler 2010 also provides RTL designers access to IC Compiler’s floorplanning capabilities from within the synthesis environment. With the push of a button, designers can perform what-if floorplan exploration, enabling them to identify and fix floorplan issues early and achieve faster design convergence.



“For the last few years, we have used Design Compiler’s Topographical technology to find and fix design issues during synthesis to give us predictable implementation,” said Shih-Arn Hwang, Deputy Director R&D Center at Realtek. “We see Design Compiler 2010 synthesis results closely correlating to physical results, while accelerating placement in IC Compiler by 1.5X. This tight correlation between synthesis and layout, along with faster runtimes, is exactly what we need for reducing iterations and significantly shortening design schedules in 65 nanometer and smaller process technologies.”



Design Compiler 2010 includes a new, scalable infrastructure designed to deliver significant runtime speedup on multicore compute servers. It employs an optimised scheme of distributed and multithreaded parallelisation techniques, delivering an average of 2X faster runtime on quad-core compute servers while achieving zero deviation of the synthesis results.



“We’ve focused Design Compiler improvements on helping designers shorten design cycles and improve productivity,” said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. “Since the introduction of topographical technology, the impact of logic synthesis on accelerating design closure with physical implementation has grown significantly. Design Compiler 2010 continues this trend, delivering a significant decrease in iterations and reducing run times in physical implementation. We have achieved this while dramatically updating our software infrastructure to best utilise the latest microprocessor architectures.”