Synopsys Delivers 2X Speedup for Implementing and Verifying Functional ECOs

Complex designs often undergo multiple functional ECOs late in the design process due to changing specifications and functional errors. Each ECO change can adversely impact schedule and predictability of design closure, which causes designers to invest days trying to minimize the impact of every change to the design. This process can add weeks in the late stages of the design cycle.

With the new ECO capabilities in Formality Ultra, we can cut in half the time needed for implementing functional ECOs and shorten our design schedules, said Bruce Fishbein, vice president of NCD IC Engineering at Cavium Inc. It will also enable us to implement more complex functional changes as ECOs rather than wait for the next derivative of the design. We are planning to deploy Formality Ultra on our next project.

The new Formality Ultra adds advanced matching techniques that visually highlight the mismatch between the RTL and netlist representations of a design, allowing designers to efficiently zoom in on the changes required to implement an ECO. In addition, a new multi-point verification technology very quickly checks multiple changes made to the design enabling designers to verify the correctness of their ECOs in a matter of minutes on multi-million instance designs.

Designers worldwide rely on Formality's equivalency checking technology to verify their complex, high-frequency designs without sacrificing chip performance or design schedules, said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. Formality Ultra extends this technology to address another key challenge they face – functional ECOs. It enables designers to significantly reduce the time and effort required to implement those ECOs, increase schedule predictability and close their designs on time.