Synopsys - DesignWare Protocol Analyzer for verification of SuperSpeed USB 3.0-based designs

The DesignWare USB 3.0 Protocol Analyzer is part of the DesignWare verification IP for USB 3.0. It displays the protocol traffic generated from simulation runs using the DesignWare USB 3.0 verification IP transactors in a high-level color-coded summary view and a more detailed symbol-view of the individual packets and payloads. Debug is accelerated by allowing designers to easily distinguish and browse traffic types and switch between the two views. The DesignWare Verification IP for USB 3.0 supports Verilog testbenches, and constrained random methodologies as defined in the proven Verification Methodology Manual (VMM) for SystemVerilog.

“The DesignWare Protocol Analyzer allows us to browse protocol activity and makes it much faster and easier to debug protocol errors and latency issues,” said Jessy Chen, executive vice president of Realtek. “As we develop and bring SuperSpeed USB 3.0 integrated products to the market, it is important that our engineers have the right tools to accelerate investigation of protocol behavior.”

“Verification engineers are faced with tremendous challenges as standard interfaces on SoC designs increase in number and complexity,” said John Koeter, vice president of marketing for the Solutions Group at Synopsys. “By easing the verification effort with the new DesignWare Protocol Analyzer, Synopsys is leading the effort to help Realtek and other early providers of USB 3.0 solutions bring innovative products to market faster and with less risk.”