Synopsys and TSMC streamline multi-die system complexity

The Synopsys Multi-Die System solution includes 3DIC Compiler, a unified exploration-to-signoff platform that delivers the highest levels of design efficiency for capacity and performance. In addition, Synopsys has achieved first-pass silicon success of its Universal Chiplet Interconnect Express (UCIe) IP on TSMC’s leading N3E process for seamless die-to-die connectivity.

“TSMC has been working closely with Synopsys to deliver differentiated solutions that address designers’ most complex challenges from early architecture to manufacturing,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “Our long history of collaboration with Synopsys benefits our mutual customers with optimised solutions for performance and power efficiency to help them address multi-die system design requirements for high-performance computing, data centre, and automotive applications.”

“Through our strong alliance with TSMC, we provide a comprehensive and scalable solution for unprecedented performance and efficiency in multi-die system designs,” said Sanjay Bali, vice president of Strategy and Product Management for the EDA Group at Synopsys. “The ability to explore, analyse, and signoff multi-die system designs in a unified platform using a common standard like 3Dblox 2.0, along with the silicon proof of the Synopsys UCIe PHY IP on the TSMC N3E process, enables customers to accelerate system design from early architecture all the way to manufacturing.”

Synopsys 3DIC Compiler, certified by TSMC, enables full-stack designs using the 3Dblox 2.0 standard and 3DFabric technologies in a unified die/package exploration, co-design, and analysis platform. Its integrated system analysis capability allows co-optimisation of thermal and power integrity aligned with 3Dblox 2.0 system prototyping, which helps to ensure design feasibility. Synopsys and Ansys continue to collaborate and deliver signoff accuracy for system-level effects with the integration of Synopsys 3DIC Compiler and Ansys multi-physics analysis technologies. Synopsys 3DIC Compiler also interoperates with the Synopsys Test products to ensure volume test and quality.

Adopted by multiple companies, Synopsys’ UCIe PHY IP on the TSMC N3E process has achieved first-pass silicon success, helping designers efficiently integrate the de facto standard for die-to-die connectivity into their multi-die systems. The results demonstrate maximum power efficiency and performance at 16Gbps, scalable to 24Gbps, with robust link margins. Supporting standard and advanced packaging, the complete UCIe controller, PHY and verification IP solution offers test, repair, and monitoring capabilities to help ensure multi-die system reliability even during in-field operation. In addition, Synopsys provides a complete IP solution for HBM3 to address the high memory bandwidth requirements of multi-die systems. The combination of IP and 3DIC Compiler enables higher productivity and lowers IP integration risk by automating routing, interposer studies, and signal integrity analysis in support of the 3Dblox 2.0 die-to-die feasibility studies.