Synopsys Advances Mixed-Signal Verification with New CustomExplorer Ultra

CustomExplorer Ultra provides a comprehensive regression and analysis environment to increase verification productivity and streamline the verification process for analog and mixed-signal designs. The combination of CustomExplorer Ultra and Synopsys' CustomSim™/VCS® mixed-signal verification solution provides design teams with a high-performance, productive mixed-signal simulation and regression management environment for complex system-on-chip (SoC) verification.



With the increasing number of mixed-signal circuits in SoCs, verification teams are demanding a high-productivity environment to significantly reduce the complexity of mixed-signal verification tasks, said Paul Lo, senior vice president and general manager, Synopsys Analog/Mixed-Signal Group. CustomExplorer Ultra complements our strong CustomSim/VCS mixed-signal verification solution to provide design teams with a scalable solution to tackle the verification challenges of complex mixed-signal SoCs.



Regression Automation



CustomExplorer Ultra is seamlessly integrated with the CustomSim/VCS mixed-signal verification solution. Multiple testbench and corner configurations can easily be set up, and simulation jobs are automatically queued and submitted to the server farm. Simulation job distribution and monitoring gives real-time status of multiple jobs running on multiple machines, providing quick feedback if problems are detected during simulation.



Advanced Analysis and Debug



Simulation results are collected, processed and presented in a spreadsheet-style display, providing an easy-to-read visual summary of the verification tests. Pass/fail results are indicated in the display, and the results can be filtered by design, design variables, equation results, or equation expressions. The unique Waveform Compare technology in CustomExplorer Ultra can be used to compare simulation results to a known-good waveform, saving considerable analysis time. The CustomExplorer Ultra debug environment offers complete SPICE linting, design hierarchy file browsing and signal tracing, as well as cross-probing between netlists, waveforms and interactively-generated connection visualization for rapid debugging. CustomExplorer Ultra is integrated with Custom WaveView (included), enabling waveform cross-probing and sophisticated waveform measurements. Together, these features aid designers in rapidly performing customized advanced analyses in a powerful design verification and debugging environment for analog and mixed-signal designs.



Heterogeneous Netlists Assembly



Netlists can be imported from a variety of heterogeneous sources and assembled into a single simulation netlist for verification using the configuration manager; SPICE, Verilog, Verilog-A, Verilog-AMS and SystemVerilog formats are supported. CustomExplorer Ultra's ability to assemble heterogeneous netlists from multiple sources greatly enhances the automation of mixed-signal verification.