Siemens Solido Design Environment software

IC engineering teams must increasingly adapt to a new era of substantially higher design complexity driven by demand for compelling, highly differentiated applications across industries including wireless, automotive, high-performance computing (HPC), and internet-of-things (IoT). Siemens’ new Solido Design Environment software has been developed to help circuit designers address this challenge, delivering a unified approach for custom IC design and verification that can help designers to achieve high overall design quality and reduce time-to-market, while optimising for these inter-dependent tradeoffs.

The newest addition to Siemens’ intelligent custom IC verification platform, the Solido Design Environment software, features AI technology and cloud deployment readiness. The Solido Design Environment software provides a single, comprehensive cockpit that handles nominal and variation-aware analysis, including SPICE-level circuit simulation setup, measurements and regressions, as well as waveforms and statistical results analysis.

Using AI technology, the solution can help users identify optimisation paths to improve circuit power, performance, and area, as well as to perform production-accurate statistical yield analysis at a fraction of runtime compared to brute-force methods. It also features new Additive Learning technology that assists in significantly boosting performance for design and verification teams, producing smarter and faster AI decisions and analysis using retained AI models. With these advanced capabilities, the Solido Design Environment software can help to achieve verification accuracy up to 6 sigma and higher yield at speeds orders of magnitude faster than brute-force Monte Carlo, while helping to significantly improve coverage and accuracy.

“Semiconductor content is growing dramatically in a multitude of applications,” said Amit Gupta, vice president and general manager of the Custom IC Verification division at Siemens Digital Industries Software. "Engineering teams must adapt to higher design complexity and increasing variation effects, while meeting power, performance, area, and yield targets. With cutting-edge AI technology for signoff variation analysis seamlessly integrated into an intelligent, cloud-ready design environment, Solido Design Environment software represents a breakthrough for custom IC design, providing disruptive advantages for standard cell, memory, and analog IP design teams.”

Early customers are experiencing significant benefits. Using the new solution, SK hynix Inc., a top tier global provider of advanced memory and sensor technologies, significantly reduced the time it takes for them to go from initial design to production. “Verification accuracy and turnaround time are key factors in our design flow, as we create the next generation of memory technology,” said Mr. Do Chang-Ho, head of Computer Aided Engineering at SK hynix. “Siemens’ Solido Design Environment software has delivered brute force-accurate variation analysis coupled with powerful and easy-to-use design optimisation, which has significantly reduced the time it takes for us to go from initial design to production.”

Other industry players on Solido Design Environment

“The Solido Design Environment software is a clear example of how Siemens EDA listens to their users and develops solutions that empower users to achieve better results,” said Sam Bagwell, Director of US Design Services for Forza Silicon. “Our designers use Solido Design Environment software as their simulation environment when custom designing, low-noise, high-resolution, high speed CMOS image sensors for a wide range of applications including cinematography, machine vision, automotive, AR/VR, and more. We have had an outstanding experience with the solution, due to its productivity-boosting design workflows, intuitive results visualisation, and excellent user support.”

“We have been using the Solido Design Environment software in our production custom design methodology, and it has exceeded our expectations,” said Patrick Camilleri, Co-founder and Vice President of Engineering at Crypto Quantique. “Thanks to the solution’s flexibility to adapt to our use models, we were able to integrate it into our existing methodology with ease and take advantage of its tool-assisted workflow capabilities to boost our design efficiency.”

“Solido Design Environment’s variation-aware verification capabilities have significantly benefited our design flow," said Randy Caplan, Chief Executive Officer for Silicon Creations. "Its ability to quickly and accurately identify potential issues at high sigma, as well as to provide insights on optimising our designs to work at a high degree of robustness, have been helpful to designers as we continue to provide world-class design IP to our customers.”