Siemens debuts advanced ESD verification for IC design

Combining the power of Siemens’ Calibre PERC software with the SPICE accuracy of its AI-powered Solido Simulation Suite, it provides a fast and highly accurate method for checking compliance against foundry rules spanning all phases of IC design.

Supporting full-chip level verification, the solution helps engineering teams better manage design and manufacturing challenges in both established and emerging process nodes. Its context-aware checks can help to improve the accuracy of results, while reducing turnaround time for physical, circuit, electrical and reliability IC design verification.

The solution’s context-aware checking allows design teams to verify ESD paths quickly, in time to secure waivers from foundry rules that can lead to smaller die sizes and optimised designs – ultimately helping design teams quickly arrive at data driven decisions 8x faster than current methods.

Foundry ESD rules are designed to prevent ESD failures, while accommodating the diverse design styles submitted by fabless companies globally. However, these rules may be overly conservative for specific design styles and mission profiles. By rapidly identifying and simulating ESD paths that might fail foundry rules with detailed transistor-level breakdown models, this Siemens’ new software identifies at-risk paths with SPICE-level precision, allowing for fast, targeted and automated fixes.

“Siemens’ new context-aware ESD simulation solution can help deliver accurate reliability assessment for complex IC designs,” said Silicon Labs’ Michael Khazhinsky, Principal ESD Engineer of Central R&D. “The push-button solution integrates dynamic simulation results from Solido into a full-chip Calibre PERC result that can be used to quickly determine if designs are electrically robust. In the event of circuit errors, this Siemens solution identifies nets and devices that need to be improved.”

Automated context-aware IC design verification can now become a best practice, helping the quick delivery of reliable and timely IC chips to market. Featuring functionalities such as automated voltage propagation, voltage-aware design rule checking, and the integration of physical and electrical information within a logic-driven layout framework, it helps design teams working to tight schedules.

"By leveraging automated context-aware checking, Siemens is empowering design teams to address more quickly the complexities of modern IC design reliability verification," said Michael Buehler-Garcia, Vice President of Calibre Product Management at Siemens Digital Industries Software." This integration combines the strengths of our dynamic simulation from Solido and sign-off level ESD verification in Calibre PERC. Our integrated solution speeds up the verification process while at the same time ensuring the reliability of IC designs, helping our customers achieve their goals more efficiently. This is the first in a series of solutions that Siemens plans to provide that leverage offerings from different elements of our software portfolio to speed overall design cycle time."