Reduce semiconductor process development time

The generation of SPICE models, design rules and parasitics from TCAD and lithography simulations allow the creation of early process design kits to evaluate the performance, power, area and cost of a new process node.

Dr. Anda Mocuta, Director, Technology Solutions and Enablement, imec, commented: "To meet the performance, power, area and cost targets of the 10nm process node and beyond, semiconductor manufacturers need to evaluate a larger number of process options, device architectures and materials and account for design criteria in selecting the best options. The new simulation solution from Synopsys enables seamless links in the DTCO chain and helps speed up the down-selection of technology options."

In the past, the development of new process nodes was focused on the scaling and optimisation of a single device architecture, the planar MOSFET and a single material, silicon. With the introduction of FinFET in logic and 3D-NAND in memory, the complexity of new process nodes increased significantly. This complexity will only accelerate as future process nodes will need to evaluate and select among a larger number of processes, device architectures and materials.

Increasing complexity of new process nodes

• To meet the expected gains in performance, power and area with each new process node, current and next-gen lithography technologies must be evaluated from the point of view of critical pitches, pattern printability and layout constraints.
• Achieving transistor performance and power targets requires consideration of new device architectures, such as nanowire FETs and tunnel FETs, with high-mobility channel materials as an option.
• Selection among this exploding number of process, device architecture and material options is further complicated by complex interactions between design rules, interconnect parasitics and transistor performance and the unavailability during the early stages of research of wafer data from which to build or calibrate models.

Pre-wafer simulation solution benefits

• Combines the production-proven Sentaurus TCAD, Process Explorer and Sentaurus Lithography tools with new tools for automated variation-aware SPICE model extraction.
• Enables the creation of PDKs from simulation data so design teams can assess the impact of technology options on circuit performance and area earlier than currently possible.
• By starting design-technology co-optimisation earlier, process development teams can reduce expensive and time consuming wafer-based iterations when selecting the right options to meet process node performance, power, area, cost and timeline targets.

"Working closely with our customers, we have developed a pre-wafer simulation solution to help our customers deliver process nodes faster. Our unique combination of TCAD, litho and SPICE simulation enables us to deliver a complete solution to address the challenges in technology development of advanced process nodes," added Dr. Howard Ko, Senior Vice President and General Manage, Silicon Engineering Group, Synopsys.