Place & route software boosts throughput tenfold

Samsung and Synopsys have partnered on IC Compiler II since the early days and have observed first-hand the game-changing benefits of up to five times faster implementation through several successfully completed tapeouts. Having observed compelling turnaround time and QoR benefits with IC Compiler II, Samsung is actively deploying IC Compiler II for place and route and is rolling out the 15.06 release throughout Samsung.

The 15.06 release offers cutting-edge capabilities such as the industry's only multi-level design planning for faster closure, advanced total power optimisation and innovative context-aware clock tree synthesis techniques for an additional 10% reduction in total power and up to 5% smaller area. With the 2015.06 release of IC Compiler II, Synopsys continues to strengthen its "power of 10X" solution for widespread deployment across the physical design community.

IC Compiler II is Synopsys' next-gen place and route solution, designed from the ground up to deliver the highest productivity and best QoR for designs across all process nodes. This full-featured, production-ready, netlist-to-GDSII implementation system is built on a brand new multi-threaded infrastructure. It offers ultra-high capacity design planning, unique clock-building technology and patented global analytical optimisation capabilities.

These innovative technologies enable IC Compiler II to address today's hypersensitive time-to-market needs by delivering five times faster runtime along with half the iterations required to achieve target performance, together providing a ten times boost in throughput. The leap forward in productivity realised with IC Compiler II is continuing to deliver transformational benefits to physical designers worldwide.

The 2015.06 release of IC Compiler II introduces several advanced technologies to enable additional QoR and throughput advantages for its growing customer base. Innovative capabilities like multi-level design planning enable seamless handling of complex multi- hierarchy design requirements, resulting in faster design closure. Techniques such as total power optimisation and context-aware clock tree synthesis deliver smaller area and reduce total power, benefits that are critical to designing at emerging technology nodes. This latest release also includes advanced Electro-Migration (EM) optimisation, native support for mesh and multi-source topologies, and technologies for 10nm node readiness.

"It is rewarding to see top semiconductor companies such as Samsung actively deploying IC Compiler II for their physical design needs," said Antun Domic, Executive Vice President and General Manager, Design Group, Synopsys. "Our 2015.06 release marks yet another milestone for IC Compiler II which has seen an unprecedented level of adoption across more than 30 companies, with the list continuing to grow rapidly."