Place and route product incorporates look-ahead technology

The product's predecessor, released in 2013, also featured look-ahead technology. This included the use of actual route topologies to identify and avoid congestion, faster wires to boost timing and improved modeling to accurately predict downstream wire delays.

More look-ahead technologies are featured within the company's recent release, and include accounting for downstream effects such as crosstalk at the pre-route stage and performing virtual optimisations during placement for improved timing. To more accurately account for the timing impact of signal integrity and detailed wiring, the product also features CCD, a technology to increase on-chip clock frequency. With this technology, circuits are up to 5% faster. 

To minimise the number of ECOs and implement them with minimal layout perturbation, the IC Compiler operates with Synopsys' PrimeTime. The product also improves signoff correlation through a consistency checker, which automatically identifies and resolves differences between the signoff and place-and-route environments. For faster design closure, the product provides expanded coverage of the consistency checker and multivoltage-aware on-route ECO implementation.

Several second order effects that are essential to delivering quality results on FinFET-based designs are also addressed by the product. To achieve the maximum total power savings and meet timing requirements, dynamic power is optimised simultaneously with leakage power, timing, area and routability. The tool also retains the benefits of miniaturisation by addressing the pin accessibility challenge for small, highly optimised cells. To reduce wire resistance, IC Compiler features parametric on-chip variation, which is a lightweight statistical margining approach to generate higher performance circuits.

"Cavium is a market leader in high-performance processors used to power a wide array of networking applications around the world," said Anil Jain, Corporate Vice President, IC engineering at Cavium. "We have long relied on IC Compiler to provide us with new, leading-edge technologies that enable us to achieve the best performance across all our complex and challenging designs. The latest release helps us further our leadership position in the marketplace."

"As a leading provider of high-performance SoCs, Cavium has been an early adopter of each emerging process node while pushing the envelope on performance and power," said Antun Domic, Executive Vice President and General Manager, Design Group at Synopsys. "Our close collaboration has helped drive many state-of-the-art technologies in IC Compiler and led to its widespread deployment as the standard place-and-route tool across all of Cavium."