PHY IP targets 16nm FinFET Plus processes for mobile SoCs

9th April 2015

Synopsys Inc

Siobhan O'Gorman

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To enable designers to integrate required functionality in mobile and enterprise SoCs with less risk, Synopsys has introduced a portfolio of DesignWare PHY IP for TSMC's 16nm FinFET Plus (16FF+) processes. The silicon success of the DesignWare IP in TSMC's 16FF+GL and 16FF+LL processes enables designers to accelerate the development of SoCs that incorporate embedded memories and interface IP for USB 3.0, 2.0 and HSIC; PCIe 4.0, 3.0 and 2.0; SATA 6G; HDMI 2.0; MIPI D-PHY; DDR4/3 and LPDDR4/3/2 protocols on TSMC 16FF+ processes.

The DesignWare STAR Memory System product is a comprehensive, integrated test, repair and diagnostics solution that supports Synopsys and third-party embedded memories. TSMC uses DesignWare STAR Memory System to characterise all of its 16FF+ memory compilers. The optimised test and repair algorithms maximise test coverage while reducing test time, lowering test cost and improving manufacturing yield. Synopsys also provides DesignWare Logic Libraries for the TSMC 16FF+ processes that include 7.5-, 9- and 10.5-track libraries, power optimisation kits and High Performance Core kits. All Synopsys embedded memories and logic libraries, including those on TSMC 16FF+ processes, work seamlessly with the IC Compiler II place-and-route system that accelerates throughput and improves quality of results.

"TSMC's long history of collaboration with Synopsys has provided designers with silicon-proven IP on advanced processes to speed development of SoCs for mobile and enterprise applications," said Suk Lee, Senior Director, Design Infrastructure Marketing Division, TSMC. "The availability of DesignWare IP for TSMC's 16FF+ processes enables designers to benefit from the technology's performance, power and area while accelerating their time-to-volume production."

"As the leading provider of physical IP for FinFET processes, Synopsys continues to invest in IP that helps designers take full advantage of the latest processes' speed and power characteristics while implementing high-quality, proven IP in their SoCs," said John Koeter, Vice President, Marketing, IP and Prototyping, Synopsys. "Our close collaboration with TSMC mitigates risk for designers integrating interface, embedded memory and logic library IP into high-performance, low-power SoCs using TSMC's 16FF+ process."

The DesignWare USB 3.0 and 2.0, 16G PHY, PCIe 4.0, 3.0 and 2.0, SATA 6G, HDMI 2.0, MIPI D-PHY, DDR4 multiPHY (including DDR4/3 and LPDDR4/3/2), logic library and embedded memory IP for TSMC's 16FF+ process, as well as STAR Memory System and IC Compiler II, are available now.