PCIe 3.1 controller & PHY IP cut active & standby power

In addition, supply under drive, a novel transmitter design and equalisation bypass schemes cut active power to well below 5mW/Gb/lane while meeting the PCIe 3.1 electrical specification. By providing a controller and PHY IP solution for PCIe technology that is optimised to deliver the lowest power consumption, Synopsys enables designers to incorporate the necessary functionality into their SoCs and extend the battery life of mobile devices.

The DesignWare PHY IP for PCIe 3.1 technology exceeds required PCIe channel performance with multi-phase-locked loops, feed forward equalisation, continuous time linear equalisation and programmable decision feedback equalisation to enhance signal integrity across high loss and bumpy channels. separate refclk independent SSC, reference clock forwarding and PCI Express architecture aggregation and bifurcation provide flexibility and scalability for high-speed SoCs. The PHY's Automatic Test Equipment test capabilities, small area and optional wirebond packaging reduce overall BOM cost.

As part of the complete solution, the DesignWare Controller IP for PCI Express 3.1 specification supports L1 sub-states in conjunction with power islands or retention cells for up to 95% lower leakage power during standby mode and very low exit latency, enabling faster wake up time. To reduce active power, the controller supports system-level power management features including Latency Tolerance Reporting, Optimised Buffer Flush/Fill and Dynamic Power Allocation.

In addition, Synopsys Verification IP for the PCIe architecture combined with SystemVerilog source code test suites support the validation of low-power scenarios. The VIP provides controls to enter, switch between and exit low-power sub-states. It monitors low-power states, and the test suites provide a dedicated set of tests to validate L1 sub-states functionality.

“As a PCI-SIG member for more than a decade, Synopsys has helped advance PCIe technology,” said Al Yanes, Chairman and President, PCI-SIG. “Products such as its low power IP solutions support the adoption of the PCIe architecture in SoCs used in mobile applications.”

“More features, faster performance and longer battery life are driving the evolution of mobile devices in the consumer electronics ” said John Koeter, Vice President of Marketing, IP and Prototyping, Synopsys. “By providing the industry with the lowest power PCI Express IP solution, Synopsys is helping designers meet the stringent technology requirements of today's mobile applications and accelerate their time-to-market.”

The low-power DesignWare Controller and PHY IP for PCIe 3.1 technology are available now. The Verification IP for PCIe 3.1 architecture as well as DesignWare IP Prototyping Kits for PCIe 3.1 Root Complex and for PCIe 3.1 Endpoint are also available now.