New NVM IP cuts power consumption by up to 90%

21st November 2013

Synopsys Inc

Staff Reporter

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The new DesignWare AEON Multiple-Time Programmable (MTP) Ultra Low-Power (ULP) Non-Volatile Memory (NVM) IP has today been made available by Synopsys. Optimized for the stringent power and area requirements of wireless and RFID/NFC ICs, the DesignWare AEON MTP ULP NVM IP cuts power consumption by up to 90% compared to the previous generation by offering a single-bit read capability, read operation down to 0.9V and peak current under 10uA during erase and programming. This reduction in power consumption enables battery life to be extended in mobile systems, increased RFID/NFC tag sensitivity and reduces tag size by allowing the use of smaller antennas.

The DesignWare AEON MTP ULP NVM IP offers single-bit read capability to give designers additional flexibility in setting power/timing tradeoffs, which can depend on the peak current and read time requirements. To reduce factory programming test costs, the IP includes a fast programming mode that cuts programming time by 70 percent compared to the previous generation. With up to 100,000 write cycle endurance, RFID and NFC designers using DesignWare AEON MTP ULP NVM IP can have confidence that their products can be reprogrammed many times for extensive reuse. In addition, the IP integrates critical high-voltage generation and distribution circuitry to simplify integration and reduce system cost and area.

"Offering ULP NVM IP on our high-volume 180 nanometer CMOS process will enable our customers to reduce their overall system costs and meet the ultra low-power requirements of RFID and NFC tags," said Yit Loong Lai, senior vice president at SilTerra. "DesignWare NVM IP aligns well with our process technology to deliver an ideal combination of density, speed, and enduring performance to power future Internet of Things-related applications."

"To achieve their systems' power and cost objectives, designers in the competitive wireless and RFID/NFC tag markets need the lowest power and smallest area NVM IP for their ICs," said John Koeter, vice president of marketing for IP and systems at Synopsys. "Synopsys DesignWare NVM IP, the industry's broadest portfolio of CMOS MTP IP, has shipped in well over three billion chips and over 40 process nodes. With the new DesignWare AEON MTP ULP NVM IP, Synopsys is building on its years of NVM technology leadership to deliver proven IP that lowers integration risk and speeds time to market."

DesignWare AEON MTP ULP NVM IP is available now in the 180 nanometer process node.