New eTools 8.0 Software Simplifies 45nm ASIC Design

3rd December 2009

eASIC

ES Admin

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eASIC Corporation, a provider of NEW ASIC devices, today announced the immediate availability of its eTools 8.0 software suite for implementing 45nm Nextreme-2 designs. The eTools 8.0 tool suite delivers a robust ASIC grade design flow with the simplicity, ease of design, and a cost point that is normally associated with FPGA design tools. By focusing on ease-of-use, and low cost of entry, eASIC is now enabling designers to make a seamless transition to adopting Nextreme-2 devices as a lower cost and lower power alternative to FPGAs and a lower NRE alternative to traditional ASICs.

The eTools 8.0 software suite includes a number of new capabilities that simplify the transition path for designers looking to adopt the advantages of Nextreme-2 devices. These include a user friendly GUI-based design environment (Design Navigator), IP-wizards that facilitate easier integration of IP blocks; a new power estimation tool that enables power estimation based on the RTL; and an easy to use floor planning tool for making optimal macro placements. Designers have the option of performing synthesis using Magma Talus RTL or Synopsys DC tools.

Unlike traditional standard cell ASIC flows, the eTools 8.0 flow enables designers to focus their efforts on achieving their desired functionality and timing and not on arduous complex deep submicron ASIC tasks such as power mesh design, signal integrity, test insertion, DFM (design for manufacture) and clock insertion. As a result, designers are able to rapidly progress from their initial RTL to a netlist-level handoff to eASIC. Nextreme-2’s unique and patented single-via based configuration technology enables eASIC engineers to rapidly tape-out and deliver prototypes in 6 to 8 weeks.

“eASIC is committed to the goal of making ASIC design achievable and affordable for the masses. We are seeing more and more FPGA designers use our technology to reduce the cost and power of their designs. With eTools 8.0 we are taking a giant step on the ease-of-use axis, thus enabling designers to create a rapid, low cost, low risk path to ASIC, said Dr. Ranko Scepanovic, Senior Vice President, Software and Advanced Technology at eASIC Corporation.