MIPI D-PHY IP operates at 2.5Gb/s per lane on TSMC 16FF+ process

The DesignWare MIPI D-PHY operating at very high speeds on the 16FF+ process, enables designers to meet their power and performance requirements while ensuring interoperability with the latest image sensors and displays. Synopsys' silicon-proven D-PHY IP is compliant with the MIPI D-PHY v1.2 specification and delivers 50% lower power and smaller area compared to other competitive solutions.

Jurgen Beck, Vice President and General Manager, Keysight Technologies, commented: "Keysight and Synopsys collaborated to validate the performance and compliance of the DesignWare MIPI D-PHY IP, helping designers lower the risk of incorporating the IP into their SoCs. This industry first demonstration underscores both companies' commitment to providing designers with high-quality IP and testing solutions that enable them to meet their design requirements and achieve silicon success."

"As Chair of the MIPI D-PHY Sub-Group, Synopsys is leading the development of the specification and closely collaborating with the Working Group members to drive adoption. Demonstrating its MIPI D-PHY v1.2 IP running at 2.5Gb/s gives designers confidence in their ability to integrate the DesignWare MIPI D-PHY in their SoC designs today," said Joel Huloux, Chairman of the Board, MIPI Alliance.

"Synopsys' demonstration gives designers assurance that they can incorporate DesignWare MIPI D-PHY IP into their SoC with confidence, while meeting their power and performance goals on the advanced 16FF+ process," added John Koeter, Vice President of Marketing, IP and prototyping, Synopsys. "Synopsys' MIPI IP solutions have been used in hundreds of designs. This successful track record combined with the demonstration enables designers to incorporate a high-quality D-PHY solution into their SoCs with minimal risk."

Synopsys' DesignWare MIPI D-PHY, CSI-2 and DSI IP are available now in a variety of advanced processes. The  verification IP for these interfaces is also available now