Low input output offset voltage hot insertion bus buffer

Hendon Semiconductors recently announced the release of the much-anticipated IES5502, Fast Dual Bi-directional bus buffer with hot insertion logic. Both the IES5501 and IES5502 also have compliant I2C signals. They are well suited for applications such as extending and expanding I2C, SMBus, PMBus, IPMB and other similar 2-wire bus systems.

The hot insertion logic with pre-charge on the IES5502 minimises disruptions on the ports and prevents data corruption on the bus during I/O card insertion into live backplanes. The IES5502 also features very low input-output offset voltages with a maximum of 125mV, allowing their use in a cascade or “daisy chain” fashion. Bus level translation (from 1.8V to 15V) is also incorporated into the IES5502 providing flexibility in interfacing systems of different technologies; speeds and loads simplifying the engineers design process.

The unique function of the IES5502 is it provides one of the fastest response times of such bi-directional buffers without the use of Rise Time Accelerators (RTA). The RTA when combined with low noise margins may cause glitches outside of the I2C specification. The Enable pin on the IES5502 is used to isolate sections of the bus and can be used to activate sections of the bus during system start-up.
The features of the IES5502 makes it well suited for the computing or networking systems such as backplane applications within telecommunications systems (including AdvancedTCA) where there are differences in voltage levels and speeds. It is also suited for use in Field Replacement Units (FRUs) used in either a conventional fully-bused arrangement or in radial architecture.

The IES5502 is offered in 8-pin SO and MSOP packages, all are RoHS compliant with samples available now.