Key ASIC deploys Synopsys' Design Compiler Graphical solution

Design Compiler Graphical addresses challenging requirements, such as performance, area, power and congestion, at both established and emerging process nodes. It provides IC designers with visualisation of congested circuit regions and performs automated synthesis optimisations to minimise congestion in these areas. Additionally, new optimisation technologies monotonically reduce design area and leakage power by an average of 20% while maintaining timing QoR. Design Compiler Graphical shares physical technologies with Synopsys' IC Compiler and IC Compiler II place-and-route solutions to deliver highly correlated results for timing, area, power and routability, reducing design iterations and shaving critical schedule time.

"Key ASIC's design expertise targets the critical challenges of smaller die size, functional integration and cost reduction for high-performance, low-power SoCs," said Meisie Jong, General Manager of Key ASIC's Technology Services business unit. "With Design Compiler Graphical we can identify and fix timing issues in a timely manner during synthesis and achieve higher frequency and smaller area faster. Based on our evaluation experience, we have now deployed Design Compiler Graphical as part of our production design flow."

"Key ASIC's solutions and the customers they serve require the best combination of performance, low power and small die size to be competitive and cost-effective in the market," commented Bijan Kiani, Vice President of Marketing, Design Group, Synopsys. "Design Compiler Graphical's market-leading synthesis technologies and tight correlation with IC Compiler enable Key ASIC to focus on their design expertise and unique IP while achieving the best quality of results and reduced tapeout schedules."