HAPS-60 Series from Synopsys deliver highest performance, highest capacity, pre-tested IP and unique advanced verification functionality

Built with the latest Xilinx Virtex-6 devices, the HAPS-60 series combines performance, capacity, pre-tested IP and advanced verification functionality to deliver the most comprehensive prototyping system on the market.

The lack of affordable and readily available hardware-based verification solutions has compelled designers to start hardware/software co-verification and system-level validation late in the design cycle, often leading to project delays that can result from a last-minute increase in system-level hardware and software bugs. The HAPS-60 series offers a unique combination of functionality and features that enable software development and system-level verification much earlier in the design cycle.

“By combining increased performance and capacity, pre-tested DesignWare IP and advanced verification modes with the proven Confirma software suite, the HAPS-60 series provides a cost and time-to-market advantage not possible with traditional, stand-alone hardware-based verification methods or custom-built prototyping boards,” said Joachim Kunkel, senior vice president and general manager of the Solutions Group at Synopsys. “By leveraging Synopsys’ technology leadership spanning hardware, software and IP, Synopsys provides designers with a unique prototyping platform that significantly eases their system validation and software development process.”

“Virtex-6 FPGAs provide the industry leading performance and logic capacity that enables the HAPS-60 series to meet today’s SoC verification needs,” said Mustafa Veziroglu, vice president, product solutions and management at Xilinx. “The combination of the high performance Virtex-6 devices and the new features and advanced verification functionality available in the new HAPS-60 series provides designers with an industry-leading solution for rapid prototyping.”

Key features of the HAPS-60 series include:

- Highest performance. Achieving clock frequencies of up to 200MHz, the HAPS-60 series supports applications requiring real-time interfaces such as video, cellular data or live network traffic. The HAPS-60 series, which runs up to 30 percent faster than previous generations of HAPS products, incorporates performance enhancing technologies that are not available on other solutions. This technology advantage enables full system integration and testing of all hardware and software in a real-world environment. Software developers benefit by being able to write, execute and debug code in a near real-time system-level environment, enabling the early identification and elimination of hardware and software bugs months ahead of silicon availability.

- Highest capacity. The flexible architecture of HAPS systems, combined with advanced high-capacity partitioning software and new automated high-speed Time Division Multiplexing (HSTDM), allow the HAPS-60 series to achieve greater capacities than other prototyping systems. This capacity advantage allows design teams to build prototypes of very large systems on chips (SoCs). A single HAPS board can support designs up to 18M ASIC gates (more than double the capacity of the previous generation), and multiple boards can be connected together for higher capacity.

- Pre-tested IP. With many of the DesignWare(r) IP cores such as SuperSpeed USB 3.0, PCI Express(r) and HDMI pre-tested on HAPS systems, designers benefit from having a proven solution for system-level hardware and software prototyping using the same SoC production RTL. Using the same RTL from prototype to production reduces project schedule – and risk. With pre-tested DesignWare IP, project leaders using HAPS systems can focus their engineering resources on product differentiation and system validation instead of verifying the IP portions of their prototype.

- Advanced verification functionality. The HAPS-60 series provides advanced verification functionality, previously unavailable in prototyping systems, enabling engineers to reduce verification time by using the HAPS-60 series hardware earlier in the design cycle. Built on Synopsys’ high-performance Universal Multi-Resource Bus (UMRBus) technology, new modes of verification include co-simulation through standard PLI and SCE-MI 2.0 transaction interfaces with Synopsys VCS(r) and Innovator products, C/C++ programs, and other event driven simulators.