FPGA-based system accelerates IP and subsystem prototyping

The software included with the new system accelerates prototype availability through automated translation into a HAPS-DX specific implementation. New prototyping diagnostic and fast prototyping modes reduce the RTL review time and provide up to five times faster throughput than traditional FPGA synthesis tools. Tasks such as ASIC clock conversion, regarded as time-consuming for designers, are accelerated utilizing the new HAPS clock optimization, allowing even the most complex clocking schemes to be implemented quickly in a clock-limited FPGA architecture. In addition, direct support for Synopsys Design Constraints (SDC) format and Universal Power Format (UPF) speeds the migration of the SoC's timing and power intent into the prototype.

Using HAPS Deep Trace Debug hardware in combination with Synopsys Verdi3 debug software simplifies debugging tasks, whilst the HAPS Deep Trace Debug enables storage of seconds of signal trace data using included DDR3 memory. Addressing the need for high-speed sampling and high-capacity storage, the HAPS-DX is available with flexible debug storage options. In addition, HAPS-DX's debug software seamlessly integrates with Synopsys Verdi3 advanced debug platform to provide enhanced analysis and debug visualization.

Using Synopsys HapsTrak 3 connectors and standard FMCs, designers can leverage a broad set of HAPS daughter boards to minimize the effort of assembling prototypes that connect to real-world interfaces. To speed system validation and software development tasks, Synopsys DesignWare Interface IP such as PCI Express, USB, MIPI and DDR are being pre-validated on HAPS-DX systems enabling software development earlier in the product development cycle and reducing the IP integration effort.

HAPS-DX's integrated UMRBus interface and optional transactors for ARM AMBA interconnect provide a direct connection between a HAPS-DX system and Virtualizer Development Kits generated using Synopsys Virtualizer toolset to create an integrated hybrid prototyping environment. Hybrid prototyping enables pre-RTL software development, hardware/software integration and full system validation.

"Xilinx Virtex-7 X690T FPGA devices support 11.3 Gb/s serdes data transfer rate, making them ideal for high-bandwidth and high-performance ASIC prototype designs," commented Hanneke Krekels, director of test, measurement and emulation market segment at Xilinx. "Synopsys' HAPS-DX systems accelerate prototype bring-up via adoption of the industry standard FMC I/O technology supported by our Virtex-7 X690T FPGA, allowing designers to leverage hundreds of available FMCs, including analog-to-digital/digital-to-analog converters, video imaging and motor control."

The HAPS-DX FPGA-based prototyping systems are available now to early adopters.