Design

Express Logic ThreadX Available for Tensilica’s New Third-Generation Diamond Standard Dataplane Processor Cores

20th May 2010
ES Admin
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Tensilica, Inc. and Express Logic, Inc. today announced that Express Logic's ThreadX real-time operating system (RTOS) is now available for Tensilica's new third-generation Diamond Standard dataplane processor (DPU) cores. A free demo download of the ThreadX RTOS is available on the Tensilica web site at http://www.tensilica.com/partners/operating-systems/express-logic/threadx.htm. Designed for small-footprint, demanding real-time control, the ThreadX RTOS is a perfect match for the Diamond Standard family of general-purpose, low-power cores aimed at deeply embedded control and signal processing functions.
This free download shows how efficient and configurable our ThreadX RTOS is for all of Tensilica's processors, including the recently introduced third-generation Diamond Standard cores, stated William E. Lamie, president, Express Logic. Because ThreadX is implemented as a C library, only the features used by the application are brought into the final image for that processor core. This is ideal for Tensilica's processors, which can be customized for optimum speed, power, and performance for a given application.

ThreadX is one of the most popular operating systems because it is so efficient and easy to design into deeply embedded applications, stated Chris Jones, director of strategic alliances at Tensilica. Now, with the availability of the free evaluation download, designers are able to immediately discover the inherent benefits of this operating system.

ThreadX is designed for fast real-time performance. It helps applications quickly respond to external events with its priority-based, preemptive scheduling. It is also deterministic, providing bounded real-time response regardless of the size of the application. A high-priority thread starts responding to an external event in the amount of time it takes to perform a highly optimized ThreadX context switch - under 250 nanoseconds on a DPU core running at 1GHz. It is also small with a minimum kernel size under 2K bytes.

Tensilica's Diamond Standard series DPU family covers a broad range of embedded control performance with synthesizable cores ranging from a very small 32-bit ultra-low-power, cache-less RSIC DPU to a powerful high-performance 3-issue VLIW processor.

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