Estimator Tool Guides Designers to Energy-Efficient SOC Architectures

“Xenergy will naturally appeal to designers of portable, battery-driven devices such as cellular phones and personal media players, but also to designers of complex SOCs in home entertainment and networking devices where heat is becoming a huge issue,” stated Chris Rowen, Tensilica’s president and CEO. “Tensilica is the first company to provide a realistic way to easily estimate the overall energy impact of different processor configurations and extensions together with application code tuning on each processor with its memory subsystem. The improvement in power at the architectural level is quite dramatic and productive, often dwarfing the power savings painfully achieved at the RTL and physical design levels.”

Total energy to complete a task (power dissipated over time taken for the task to complete) can be dramatically reduced by customizing a Tensilica Xtensa processor. Sample results show that with identical process technology, the energy improvement from processor customization can range from 2x to 83x.

The new Xenergy energy estimator works by computing a power-consumption estimation per-cycle for each different instruction of an Xtensa configurable processor or Diamond Standard processor. For each user-defined instruction extension in an Xtensa processor, created using Tensilica’s powerful TIE (Tensilica Instruction Extension) language, Xenergy creates an energy estimate for the newly created instruction, including modeling the energy consumed by all locally attached memories that are active for a given instruction. Then, using the instruction profile created by Tensilica’s pipeline accurate instruction set simulator, a detailed energy consumption profile is created for the user’s specific application code.

The Xenergy tool is used during the process of configuring an Xtensa processor. Designers can immediately see the effect on total energy consumption when they add configuration options (multipliers, DSP engines, a floating point unit, and many additional configuration choices) and designer-defined instructions. They can see the effect of different interface options as well as memory subsystem options.