EDA software support for 5/4nm process technologies

Featuring exceptional power, performance and area (PPA), Samsung’s new 5nm FinFET processes include enhancements which, together with smaller 5nm geometries, enable performance improvements compared to previous process nodes.

“Samsung and Mentor have an established track record of collaboration to enable our mutual customers to fully leverage the Calibre solution. Now both Calibre and AFS are certified for the very latest Samsung Foundry processes,” said Jongwook Kye, Vice President of Design Enablement Team at Samsung Electronics. “The combined expertise of Samsung Foundry and Mentor provides designers the ability to develop and quickly validate innovative ICs for a variety of high-growth markets and applications.”

The Mentor tools in addition to Calibre nmDRC achieving Samsung Foundry certification for these new foundry processes include:

• Calibre xACT: which addresses the technical challenges associated with advanced nanometer design, including multi-patterning, FinFETs, local interconnect, higher complexity and tighter constraints. Its unique hybrid engine delivers field-solver accuracy essential for detailed 3D structures like FinFETs, plus fast throughput for rapid turnaround of full-chip designs.
• Calibre YieldEnhancer: featuring SmartFill and engineering change order (ECO) fill capabilities, which allow customers to control design planarity and reduce turnaround time across multiple design iterations. Calibre YieldEnhancer also helps customers boost design reliability by reducing IR drop with an automated PowerVia flow. Samsung worked with Mentor to customise this flow for the maximum insertion of vias for their leading-edge technologies. 
• Calibre PERC: which employs a unique, integrated analysis of both the physical layout and the netlist to automate complex reliability verification checks. The latest Samsung Foundry Calibre PERC Design Kit for 5/4nm processes provides additional verification checks, allowing customers to address challenges associated with electrostatic discharge and latch-up reliability.
• Calibre nmLVS: which serves as the front-end to any Samsung Foundry extraction flow. Calibre nmLVS continues to address growing layout complexity requirements and the increasing demand of advanced computations necessary for design teams to verify even the most complex of circuits while still achieving desired runtimes for advanced process node designs.
• Calibre RealTime Digital and Custom interface platforms: which enable immediate signoff-quality DRC checking in digital and custom design flows, using the same Samsung Foundry-qualified design kits used by batch Calibre. The interfaces provide significant productivity advantages during DRC closure for both advanced and mature-node designs, enabling customers to quickly optimise their manual DRC fixes and use the time saved to focus on meeting power, performance and area goals.
• Mentor’s AFS platform: which has been optimised and certified for accuracy at Samsung’s 5/4nm processes to enable system-on-chip (SoC) designers to complete circuit verification with confidence. The AFS platform is enabled in Samsung Foundry’s device models and design kits. Mutual customers rely on the AFS platform to deliver nanometer SPICE accuracy while verifying analogue, RF, mixed-signal, memory, and custom digital circuits faster than with traditional SPICE simulators.

“With its newest processes, Samsung Foundry continues to deliver highly innovative technology for the manufacture of even the most sophisticated of IC designs,” said Michael Buehler-Garcia, Vice President of Product Management, Calibre Design Solutions for Mentor. “We are pleased to collaborate with Samsung Foundry as critical design elements of their innovative solutions help enable our mutual customers to design and manufacture advanced ICs.”