eASIC eTools 8.1 Design Suite Reduces Design Time by 40%

New features and utilities within eTools 8.1 focus on reducing design conversion and implementation time, while enhancing the overall quality of results. The rich tool suite now includes a complete floorplanner with interactive regioning capability, and a powerful new detailed placer based on a set of new advanced proprietary algorithms that are optimized for eASIC’s single via customization logic architecture. Both utilities also combine to facilitate rapid timing closure on complex NEW ASIC designs. eTools 8.1 also includes unique capabilities that enable rapid RTL design conversion from traditional design platforms such as FPGA and ASIC.

“An increasing number of FPGA designers are using our technology to reduce the cost and power of their designs, but they want design time to be quick once they have finalized their FPGA design. With eTools 8.1 we focused on speeding up the key steps in the design process. Initial feedback indicates that we have made significant strides to help designers quickly convert and implement their designs onto Nextreme-2 and achieve their desired performance, said Dr. Ranko Scepanovic, Senior Vice President, Software and Advanced Technology at eASIC Corporation.

Unlike traditional standard cell ASIC flows, the eTools 8.1 design flow enables designers to focus their efforts on achieving the desired functionality and timing of their design, and not on arduous complex tasks such as power mesh design, signal integrity, test insertion, DFM (design for manufacture) and clock insertion encountered in ASIC design process. As a result, designers are able to rapidly progress from their initial RTL to a netlist-level, or placed-gates handoff to eASIC. Designers have the option of performing synthesis using industry standard logic synthesis tools.