Distributed processing accelerates signoff physical verification

IC Validator's high-productivity multi-processing was also used to speed up Layout Versus Schematic (LVS) correctness checking and to perform customised Design For Manufacturability (DFM) and dummy metal fill on the design.

Ofer Ezra, Principal Engineer, Mellanox, commented: "We ran our design on 28 processor cores and found IC Validator to deliver near-linear scalability, reducing DRC run time. We achieved further productivity gains by writing a customised dummy metal fill runset for IC Validator that gave us additional reliability advantages on our on-chip power distribution network."

IC Validator is a comprehensive physical verification product including DRCs, LVS checks, double-patterning checks and metal fill insertion. IC Validator's modern architecture and excellent multi-core scalability make it the signoff tool of choice for a growing number of designers developing small analogue chips to those designing the largest, most advanced digital chips.

"A growing number of companies are seeing the benefits of physical verification signoff with IC Validator. The successful tapeout of this large design reinforces the viability of IC Validator as a signoff product that enables significantly reduced time to tapeout for our customers," added Bijan Kiani, Vice President of Marketing, Synopsys' Design.