Development platform can be extended

Software development is a major part of the development of a SoC or an ASIC with an embedded processor. Cortus 32-bit processor IP cores have been designed from the outset for embedded processing applications based on coding in C or C++. The APS cores are a volume-proven basis for a wide range of applications including smartcards, video processing, smart sensors, touchscreen controllers, wireless, security, industrial control and IoT. The platform enables software developers to rapidly develop drivers and to integrate software and hardware before the SoC design is prototyped.

The Cortus FPGA board is based on the Xilinx Spartan-6 X75 and includes 1MB synchronous SRAM as well as a 32Mb SPI flash memory. The flash memory holds the FPGA configuration and can also be shared to hold the application software. A 10/100Mb/s Ethernet transceiver PHY is connected directly to the FPGA and is fully compatible with the Cortus 10/100 Ethernet MAC IP block. A USB interface provides a JTAG interface fully compatible with Cortus development tools under Windows and Linux. Additional I/O connectors enable the DDR2 memory to be up to 512Mb.

With an APS23 requiring 19% utilisation and APS25 requiring 29% utilisation, the Cortus platform provides ample capacity for all APS cores. The capacity of the Spartan-6 X75 is sufficient to allow multi-core systems to be emulated on the FPGA board. The ability to extend the memory can be used to include a USB 2.0 PHY in combination with a Cortus USB 2.0 controller in order to create a prototyping platform for embedded Linux systems. Furthermore the platform can incorporate IDEs from Cortus’ partners as an alternative to Cortus Eclipse.

All APS processor cores interface to Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. The Ethernet MAC allows the chosen physical interface to be connected using either the medium independent interface or reduced medium independent interface. Flexible memory interfaces with two independent DMA channels enable system design to ensure low CPU overhead reception and transmission without any danger of frames being lost. Hardware address filtering enables a single interface to respond to multiple MAC addresses.

“Developing drivers, porting software and validating the HW/SW interface is one of the key time-to-market challenges of developing SoCs with embedded processors,” said Christopher Kopetzky, Vice President of Engineering, Cortus. He adds, “The platform combines Cortus’ proven SW development tools with the ability to extend the board through Arduino Due-compatible shields and DDR2 memory.”

Cortus will be exhibiting at the 52^nd Design Automation Conference (DAC) in San Francisco, California from 8^th to 10^th June 2015 at booth 2503.