Design

Design tools certified for 16nm FinFET Plus production

7th April 2015
Siobhan O'Gorman
0

Synopsys has announced that TSMC has concluded 16nm FinFET Plus (16FF+) v1.0 certification and reached the first milestone of 10nm certification based on the most current DRM and SPICE model on a comprehensive list of Synopsys' custom and digital design tools. This certification enables mutual customers to deploy tools in Synopsys' Galaxy Design Platform for 16nm production designs and 10nm early engagements.

The certified platform delivers technologies including routing rules, physical verification runsets, signoff-accurate extraction technology files, statistical timing analysis that correlates with SPICE, and interoperable process design kits for FinFET processes. TSMC and Synopsys have collaborated to enhance new tool features based on both 16nm and 10nm technology requirements in Synopsys' IC Compiler II place and route solution with TSMC validation. This includes full-flow colour enablement, support for connected poly on gate oxide and diffusion edge technology, layer optimisation, low Vdd timing closure and support for signal electro-migration. The two companies are also working together to complete IC Compiler II certification for 16nm by the end of April and 10nm in June 2015.

"The combination of tool certification and our longstanding collaboration with Synopsys is enabling customers' 16FF+ production ramp-up and early engagements at 10nm," said Suk Lee, Senior Director, Design Infrastructure Marketing Division, TSMC. "With a full suite of TSMC-certified digital, signoff, and custom implementation solutions from Synopsys, our mutual customers will achieve improved performance and lower power while attaining their time-to-market goals."

"Our deep collaboration with TSMC on 16nm and 10nm FinFET processes allows our mutual customers to use silicon-proven FinFET tools to achieve predictable design closure with faster turnaround time," commented Bijan Kiani, Vice President, Product Marketing, Design Group, Synopsys. "With the latest certification for these two FinFET processes, designers can take advantage of this game-changing implementation technology for their next-generation chip designs."

Key Synopsys tools certified by TSMC include IC Compiler, IC Compiler II, IC Validator, the StarRC extraction solution, the PrimeTime signoff solution, PrimeRail and NanoTime. The DesignWare STAR Memory System, the Galaxy Custom Designer schematic editor, the Laker layout tool and the HSPICE, CustomSim and FineSim simulation products are also certified by TSMC.

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