Design tool delivers 10x physical design throughput

IC Compiler II ushers in a new era of productivity by enabling a 10X increase in physical design throughput and is already contributing to successful tapeouts at leading customers. Several of these customers will be sharing their experiences with IC Compiler II at the Synopsys Users Group (SNUG) Silicon Valley, opening at the Santa Clara Convention Center. See what early partners experienced with IC Compiler II

"From RTL synthesis to static timing to physical synthesis, Synopsys has a history of innovations that have transformed electronic design. With IC Compiler II, we are approaching another transformative juncture," said Antun Domic, executive vice-president and general manager of the Design Group at Synopsys. "Built from scratch for speed, and incorporating newly developed algorithmic approaches, this new solution offers un-paralleled improvements in throughput, opening the door to a world of new possibilities in physical design."

IC Compiler II is a full-featured place-and-route system centered on a new multi-threaded infrastructure able to handle designs with more than 500 million instances. Exemplifying its "rethink, rebuild and reuse" development strategy, IC Compiler II relies on industry standard input and output formats, as well as familiar interfaces and process technology files, while introducing innovative design storage capability. It was architected with a full chip-level focus from day one, deploying novel design planning capabilities that provide a 10X performance boost while consuming 5X smaller memory. This enables designers to quickly evaluate many floor-planning alternatives to arrive at the right starting point for implementation. Complementing these chip-level capabilities is the block-level functionality powered by a new global-analytical optimization engine, a completely new clock generator and unique algorithmic capabilities in post-route optimization, which together enable enhanced quality of results (QoR) in area, timing and power. IC Compiler II also incorporates leading technologies used in IC Compiler, such as the conjugate-gradient placer and the ZRoute router. IC Compiler II achieves its results with an average of 5X faster runtime and 2X reduction in memory over the current solution. The combination of runtime speed-ups, superior floor plans, achievable QoR and an efficient, lightweight environment enable a reduction in design iterations, further boosting design productivity.

IC Compiler II has been built in close collaboration with some of the world's leading design groups. Initial shipment starts in mid-2014.