Design rule checking solution offers expanded capabilities

“In large designs it is typical to have several FSMs controlling the workflow. However, despite the use of consistent HDL patterns to describe the FSMs, the number of coding mistakes made in the RTL descriptions is often high,” observed Sergei Zaychenko, Aldec Software Product Manager. “At Aldec, we are aiming to provide the most comprehensive rule coverage to help designers create reliable, portable, and highly readable state machine descriptions.”

Verification of RDCs, also new to the 2017.12 release of ALINT-PRO, targets issues with complex SoC reset strategies and circuits with dynamically switchable regions. For instance, a harmless looking data transfer between registers with unrelated asynchronous reset controls may end with unrecoverable metastability, unless properly addressed at the RTL design phase.

Key features

• Automatic extraction of FSM descriptions directly from VHDL and Verilog/SystemVerilog RTL code, accompanied with comprehensive FSM rule coverage
• Introduced support of RDC verification 
• Re-architected verification solution for synchronous reset signals
• Expanded Aldec SystemVerilog Design rule library with more than 20 new rule checks 
• Over 20 new rule checks and numerous existing rule enhancements that facilitate automated code reviews for VHDL designs, as well as clock/reset trees consistency with design constraints 
• Extended design constraints support with automatic topology-based SDC/ADC drafts generation that covers essential timing properties, placement hints for vendor synthesis tools, as well as block-level constraints for black boxes based on aggregated data from external net connections
• Added automatic generation of black box components for unresolved VHDL design units
• Full coverage of block-level constraints for Lattice FPGA libraries for advanced CDC analysis.