Collaboration targets NBTI degradation at 14nm node & beyond

A key concern for advanced CMOS devices, NBTI has become more critical with the introduction of HKMG processes and is a dominant reliability concern for FinFET devices, contributing to the degradation of threshold voltage, current, transconductance and other electrical parameters. Through this collaboration, IIT Bombay will conduct experiments and measurements to characterize NBTI in FinFET devices. The resulting data will be used to enhance and calibrate physical NBTI models in Sentaurus Device, Synopsys' industry standard TCAD device simulator. 

"Our research over the years has helped identify the underlying physical mechanisms contributing to NBTI. We have developed both continuum and stochastic frameworks for predictive DC and AC NBTI modeling in planar transistors. Our collaboration with Synopsys and the implementation of these models in Synopsys' Sentaurus™ Device simulator will enable modeling of NBTI in FinFETs for the 14-nanometer node and beyond," said Professor Souvik Mahapatra of IIT Bombay.

"As 14-nanometer FinFET technology evolves from the development to production phase, many of our customers are concerned about device degradation and reliability caused by NBTI. The combination of IIT Bombay's proven expertise in NBTI characterization and Synopsys' expertise in device modeling will allow us to build a stochastic model to address customer needs for simulating and analyzing NBTI effects on FinFET devices," said Howard Ko, senior vice president and general manager of the Silicon Engineering Group at Synopsys.