CERN provided with high-performance SerDes IP

23rd June 2014

Siobhan O'Gorman

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Silicon Creations has announced that CERN, the European Organisation for Nuclear Research, selected its SerDes interface IP for use in the next-generation detector in the Large Hadron Collider. CERN recently tested the SerDes output channel and found extremely low jitter levels predicting bit error rates 1,000,000,000X better than conventional SerDes 1E-12 levels.

“We selected Silicon Creations to provide us with a SerDes for the associative memory chip we plan to use in the next-generation detector in the Large Hadron Collider,” says Alberto Annovi, project leader CERN Fast Tracker Detector. “Silicon Creations support was prompt and the IP works as claimed. The link in our chip has proven robust –– our Bit Error Rate testing implies an error rate better than 10E-21 at 2Gbps, easily sufficient for our purposes.”

The Silicon Creations’ SerDes architecture has been proven in processes ranging from 180 to 28 nanometres and is available for custom, semi-custom and standards-based applications including JESD204, XAUI, CPRI, SGMII, V-by-one, Infiniband and Serial RapidIO.

“We’re honoured that CERN selected our SerDes in the Large Hadron Collider Detector processing channel,” comments Andrew Cole, Silicon Creations’ vice president of business development. “The performance they have measured matches our expectations and meets their very exacting requirements. It gives us great pleasure to have a role in such important work.”