Silicon Creations has announced that Faraday Technology has selected its UMC 55nm SP Phase-Locked Loop (PLL) IP for its SoC design in multimedia and consumer related applications. The PLL has ranges of 1MHz-1.2GHz input and 1.5MHz-2.4GHz output as well as a 24-bit fractional modulator, allowing output frequency steps below 0.01ppm.

Silicon Creations has announced that CERN, the European Organisation for Nuclear Research, selected its SerDes interface IP for use in the next-generation detector in the Large Hadron Collider. CERN recently tested the SerDes output channel and found extremely low jitter levels predicting bit error rates 1,000,000,000X better than conventional SerDes 1E-12 levels.