Calibre nmLVS-Recon to streamline IC circuit verification

Introduced last year as an extension to Mentor’s Calibre nmDRC suite, the Calibre Recon technology is designed to enable customers to rapidly, automatically and accurately analyse IC designs for errors during early-stage verification design iterations, enabling significantly shortened design cycles and faster time to market.

The Calibre nmLVS-Recon solution helps speed overall circuit verification turnaround time by helping system-on-chip (SoC) engineers, circuit designers, and IC circuit verification teams identify and resolve selected systemic errors early in the development phase.

These types of violations can consume valuable compute resources and potentially generate millions of error results, many of which are due solely to the incomplete status of the design. Early adopter customers leveraging the Calibre nmLVS-Recon solution realised more than ten times runtime improvements and three times less memory requirements when analysing early-stage designs.

“The Calibre nmLVS-Recon approach establishes an entirely new paradigm for circuit verification use models,” said Jongwook Kye, Vice President of Design Enablement Team at Samsung Electronics. “By combining the Calibre nmLVS-Recon technology with Samsung’s existing certified sign-off Calibre nmLVS design kits, our mutual customers will experience faster iterations on early ‘dirty’ designs, driving accelerated LVS verification cycles. All of this will help mutual customers tape out sooner at Samsung.”

The Calibre nmLVS-Recon technology is based on a flexible configuration framework that enables multiple use models, allowing design teams to select and analyse specific classes of circuit verification issues. The tool features automated, intelligent execution heuristics engineered to help users seamlessly navigate between a complete Calibre nmLVS signoff flow and Calibre Recon selected circuit verification checks.

With advanced options for data partitioning, design breakdown, data reuse, task distribution, and error management, the Calibre nmLVS-Recon flow can be used with any foundry/integrated device manufacturer’s (IDM) Calibre sign-off design kit ‘as is’, and on any process technology node.

Early design versions typically contain many gross systemic violations. For example, a “shorted nets” class of violation generates millions of errors and is very compute intensive. Circuit verification engineers can use the Calibre nmLVS-Recon short isolation configuration to interactively and iteratively find and fix these types of violations quickly and efficiently. This option is built-in, allowing optimal flexibility and variation in the design analysis intent, while maintaining ease of use and seamless use model transition.

Michael Buehler-Garcia, Vice President of Product Management for Calibre Design Solutions at Mentor, said: “By adding the Calibre nmLVS-Recon technology to the Calibre platform, Mentor continues to address the specific challenges our customers face when designing increasingly sophisticated ICs.

“The early design exploration that the Calibre nmDRC-Recon approach offers has already helped design teams shave hours, and in some customer experiences, even days off their circuit verification times. With Calibre nmLVS-Recon technology, Mentor now offers the same opportunity for total turnaround time reduction in circuit verification, while also helping design teams address the complexity they encounter in today’s chip designs.”

The Calibre nmLVS-Recon initial offering will be available to the market with the Calibre family release in July of 2020.