Cache coherent subsystem verification for Arteris' Ncore interconnect

With Synopsys' configurable cache coherent Network-on-Chip (NoC) subsystem verification solution, SoC teams can accelerate verification closure of their particular Arteris Ncore cache coherent interconnect configuration.

Craig Forrest, Chief Technology Officer, Arteris, commented: "The Arteris Ncore interconnect delivers enhanced configurability for heterogeneous cache coherent SoCs in multiple markets including mobility, automotive, storage and networking. Synopsys' NoC subsystem verification solution is a key enabler for our mutual customers to efficiently verify their complex SoC designs for overall productivity gains."

The Synopsys cache coherent NoC subsystem verification solution generates UVM testbench logic that integrates with Arteris Ncore interconnect testbenches, enabling connectivity of new subsystem level tests, monitors, coverage and performance tests and analysis to achieve accelerated verification closure. The cache coherent NoC interconnect subsystem solution includes subsystem level test suites to validate the coherency of the system, in addition to the correctness of data flow across the NoC. Synopsys' Verdi Performance Analyzer is natively integrated in the cache coherent NoC subsystem verification solution for functional scenarios and provides debug capabilities for performance issues across the SoC. In addition, Synopsys' Platform Architect MCO enables analysis of the Arteris Ncore interconnect subsystem models, allowing designers to optimise architecture performance and power earlier.

"We continue to work closely with industry leaders to develop the industry's first subsystem verification solution. With the Synopsys NoC solution we have enabled SoC teams to achieve accelerated verification closure with automated testbench generation and integration, as well as subsystem and performance verification," added Vikas Gautam, Group Director, VIP R&D and Corporate Applications, Verification Group, Synopsys.