Design
Avago Technologies and Xilinx Streamline Design of 10 Gigabit Ethernet Systems Using FPGAs and Optical Interconnects
Avago Technologies and Xilinx, Inc. today announced completion of interoperability testing between Xilinx Virtex-6 HXT FPGAs and Avago SFP+ and QSFP+ optical transceiver modules. The testing proves the design and interoperability of 10 Gigabit and 40 Gigabit Ethernet ports using optical interfaces from Avago with the market-leading transceiver jitter performance of Virtex-6 HXT FPGAs.
“X“Xilinx designed the GTH transceivers in Virtex-6 HXT devices to be optimized for demanding optical interfaces, and the proof of that effort is evident in our ability to support 10 Gigabit SFP+ Ethernet optical ports up to 300 meters for 10GBase-SR using modules from Avago.”
“We are pleased to offer Virtex-6 FPGA designers the option of using proven high-quality, high-performance SFP+ optics from Avago,” said Victor Krutul, Director of Marketing for the Fiber Optics Product Division at Avago. “System engineers can now design with confidence when developing systems using high-bandwidth optical interconnects and Xilinx FPGAs.”
Link verification has been completed with 10 Gigabit Ethernet SFP+ modules using both short-range and long-range fiber, as well as with 40 Gigabit Ethernet QSFP+ modules using short-range fiber. Avago is the first and only company shipping 40 Gigabit QSFP transceivers. In addition, a complete test suite to verify compatibility with the IEEE 802.3ae 10GBASE-SRand the SFP+ SFF-8431 MSA specifications has been completed using SFP+ modules with operation verified over full specified link distances of 300 meters for OM3 multi-mode fiber and 10 km for single-mode fiber.
Xilinx Virtex-6 HXT devices seamlessly interface to industry standard SFP+ and QSFP+ optical modules at line rates up to 11.18 Gbps addressing next generation application needs. Furthermore, through superior jitter performance – sub 500 fs rms random jitter at 11.18 Gbps – and signal integrity, the need for external conditioning circuitry is eliminated. The superior jitter performance provides the system designer the margin required to build robust high speed interfaces.