Altera's Quartus II 6.0 offers integrated HDL support for Aldec's Simulator

The interface provides customers with the ability to specify the format and location of functional
and timing simulation files in Quartus II software version 6.0. The integration provides mutual customers with a seamless interface to Active-HDL for quick HDL simulation set-up to support the increasingly large and more complex FPGA devices being delivered from Altera.

"With the continued growth of our customer base in the FPGA market and
Altera's ever increasing device capacity, the natural progression was
product integration to provide our mutual customers with greater
productivity," stated Dave Rinehart vice president of marketing at Aldec.
"The complexity of FPGA designs continues to rise and the integration of
Aldec's core technology in HDL simulation combined with the Altera's design
tools provides customers with an even faster track to their simulation
results," Rinehart added.

"Our Quartus II software delivers a robust and comprehensive programmable
logic and structured ASIC design flow," said Jim Smith, Altera's director of
EDA relations. "Providing an interface to Aldec's popular Active-HDL
simulator will enable our mutual customers to achieve even tighter
integration between Aldec's tool and our development environment - making
our customers' jobs easier with a seamless debugging solution."

The interface is available today and is a standard feature in both Aldec's
Active-HDL and Altera's Quartus II environments. Active-HDL is sold directly
by Aldec, Inc. in the U.S. and by authorized international distributors. For
more information, please visit www.aldec.com. Altera Quartus II development
software version 6.0 is sold directly by Altera and its authorized worldwide
distributors.