Advanced connectivity for embedded vision and the edge

The new revision brings numerous additional features, such as SerDes support for extended edge connectivity and up to 4 MIPI-CSI camera interfaces to meet the increasing demand for a fusion of embedded computing and embedded vision.

The new features are backward compatible with Rev. 2.0, which means that 2.1 modules can be integrated on 2.0 carriers. All extensions to Rev.2.0 are also optional, so all congatec SMARC 2.0 modules are automatically compatible with SMARC 2.1.

"The new SMARC 2.1 specification is an important step towards embedding MIPI-CSI camera technology, which is widely used in smartphones, firmly and for the first time within the standard of an embedded computing specification. We need this extremely cost-effective technology in order to be able to integrate it into any embedded application. For this purpose, SMARC 2.1 provides not only one or two, but up to four interfaces for comprehensive situational awareness and highest device efficiency," explained Christian Eder, Director Marketing at congatec and SGET editor of the SMARC 2.1 specification.

As current studies by Industry Research.co show, demand for machine vision cameras is growing at clear double-digit rates. Growth is particularly strong in various non-industrial applications such as surveillance, forensics, robotic surgery, intelligent traffic systems, border control and health monitoring. In addition, camera technology continues to be used for process inspections to reduce errors such as incorrect fill levels, faulty products in the production line and packaging defects.

Autonomous logistics vehicles also take up a large market share in the industrial sector. With comprehensive Ethernet support for more connectivity at the edge gaining increasing significance, two of the four supported PCIe lanes now offer two additional Ethernet ports via SerDes signals. These can also be used for vision through the connection of GigE vision cameras.

Other new features include PCIe clock request signals, which can be used to switch off unused PCIe lanes to save power, and 14 instead of 12 GPIOs (General Purpose Input/Output). In response to many requests, the specification document was also completely restructured to optimize readability.