Design

XMOS today announces its Multi-Function Audio (MFA) platform, enabling designers to address the growing demand from consumers and the music industry for higher audio quality from their professional and audiophile products. A fully featured reference design that provides the core USB audio capabilities required in next-generation audio products, the MFA platform leverages XMOS technology already in use by customers such as Meridian, OPPO, Sennheis...

Sondrel is employing secure border computing technology from Zentera Systems to ensure IP protection with the minimum of impact on its customers’ IT infrastructure. Zentera's Hybrid Cloud Technologies enable IP to be securely accessed from diverse worldwide locations, ensuring that the best available design resources can be employed to get the project done on time at the best performance. 

Cadence Design Systems has announced that a production proven host controller intellectual property (IP) for USB 3.0 has been added to the Cadence IP offering. The Cadence USB 3.0 xHCI host controller IP was originally developed by Fresco Logic, a global fabless semiconductor company that develops and markets advanced connectivity solutions.

Coverity have announced the release of version 7.5 of the Coverity Software Testing Platform, the company's integrated suite of testing solutions that enables organizations to find and fix critical quality and security issues earlier in the software development lifecycle (SDLC). With the Coverity 7.5 platform, Coverity is expanding the reach and impact of software testing by increasing collaboration between Development and Quality Assurance (QA),...

Cadence Design Systems have announced that ON Semiconductor has adopted Virtuoso Layout Suite for Electrically Aware Design (EAD) for real-time electrical analysis of parasitic and electromigration impact on its custom physical design implementation flow. With Virtuoso Layout Suite EAD, ON Semiconductor circuit and layout designers will be able to significantly reduce design time and improve the energy efficiency of their designs by immediately s...

JT users will undoubtedly be familiar with the challenges of successfully collaborating with team members using different design systems. Success depends on a seamless two-way exchange of data and a requirement to conform to company PLM procedures and engineering best practices. The two way exchange of information has been an issue for the CAD user since the earliest beginnings.

Lantiq has announced the availability of a joint reference platform with Intel for fixed LTE Broadband Router designs, offering up to 300 Mbps using Intel’s latest Cat6 capable LTE platform. The co-developed reference platform combines the Intel XMM 7260 LTE communications platform with Lantiq’s GRX330 Communications Processor and perfectly addresses the growing market demand for fixed 4G/LTE broadband services.

Synopsys has announced the availability of its VC Formal comprehensive formal verification solution, and VC CDC and VC LP advanced static checking solutions. These solutions address the growing verification challenges of complex SoCs by introducing next-generation verification technology that finds bugs earlier, faster and more accurately, as well as accelerates root-cause analysis.

Synopsys has announced the release of its DDR4/3 and LPDDR4/3/2 Verification IP (VIP) available as part of Synopsys' Verification Compiler solution and as standalone titles.  Based on 100 percent native SystemVerilog, the memory VIP includes built-in support for RDIMM and LRDIMM models, Verdi Protocol Analyzer debug capability and integrated verification plans, all designed to enable users to accelerate the verification of memory interfaces ...

Mentor Graphics and Intel Corporation have announced that Mentor’s circuit simulation and sign-off tools are fully enabled for Intel’s 14nm Tri-Gate process technology for customers of Intel Custom Foundry. Mentor and Intel Custom Foundry are providing models and rule decks for circuit simulation, design rule checking (DRC) and layout vs. schematic checking (LVS) for mobile and cloud infrastructure applications.