Multi project wafer platform suits 3D integration

These technologies include Through-Silicon-Vias (TSV), fine-pitch vertical interconnects (micro pillar with solder) and specific finishing for 3D integration like Under-Bump Metallurgy (UBM). These 3D modules will enable a wide panel of full 3D architectures, like multiple-die stacking with flip-chip, side-by-side heterogeneous integration, and 3D partitioning of different CMOS dies issued from CMP runs.

3D integration is highly complementary to traditional CMOS scaling, and has very strong potential in terms of size reduction, heterogeneous integration, miniaturisation, performance improvements and, cost reductions at the system level. The technology is now emerging in more and more applications, such as FPGA, 3D memories and MEM, and involves wafer-level processing on dedicated runs.

The platform provides for the first time access to post-process 3D technologies after regular CMOS MPW runs, for proof of concept, prototypes and/or small series production. This enables a large group of users to take advantage of cost division made possible, at silicon level, by the MPW regular services followed by post-process technologies. In addition, it allows 3D-MPW users to divide the cost of post processing. This benefits a large group of customers, such as universities, SMEs, research institutes and systems integrators, that usually do not have access to the 3D modules at large foundries.

These 3D post-process technologies require very limited re-design of existing chips, and will be initially used for specific CMOS nodes available at CMP. They may be extended in the future, depending on demand. CMP is responsible for supporting, checking and compiling the customer’s requests, while IRT Nanoelec will manage the 3D post-processing.