Processors optimised for low-power embedded DSP applications

The ARC MetaWare Development toolkit supports C-language DSP programming with fixed-point data types and operator overloading. ARC EM DSP processors are based on the RISC architecture of the EM processor family, providing the combination of efficient real-time control and DSP performance required for ultra low-power, always-on devices that process audio, voice and sensor data.

The ARC EM DSP processors implement a processing pipeline that offers an optimal balance of performance, power consumption and size for a wide range of control and DSP applications. The processor cores include a unified, single-cycle 32x32 MUL/MAC unit with 40/72-bit accumulators. To deliver enhanced performance for filtering, fast Fourier transform (FFT) and other signal processing algorithms, the EM5D and EM7D feature fractional support (e.g., Q31 and Q15 data types) with saturating arithmetic, rounding and non-rounding instructions, as well as divide and square root.

Vector support provides greater processor efficiency by enabling multiple data values to be processed in a single operation. The ARC EM5D and EM7D processors deliver excellent performance efficiency, consuming as little as seven microwatts/MHz in a typical 40nm LP process technology. This high degree of performance efficiency makes the cores suited for 'always-on' voice activation in Internet-of-Things (IoT) applications. For example, Sensory Inc.'s TrulyHandsfree Voice Control software consumes less than four microwatts when executing Sensory's Low Power Sound Detection technology on an ARC EM5D processor implemented in a 28nm HPM process (logic and memory dynamic power). This enables an integrated hardware-software solution for voice activation and control with ultra-low energy consumption.

Like all ARC processors, EM DSP processors are highly configurable so that each instance can be tailored to achieve the optimum balance of DSP and RISC performance as well as power and area efficiency. In addition, ARC Processor EXtensions (APEX) technology allows designers to create user-defined instructions, enabling the integration of custom hardware accelerators that improve application-specific performance while reducing power consumption and the amount of memory required. The ARC processors' extensible architecture also helps minimise system-level latencies and silicon area by enabling memory and system-on-a-chip (SoC) peripherals to be directly connected to the processor for single-cycle access. Native ARM AMBA AHB and AHB-Lite as well as BVCI interfaces deliver efficient system throughput. An optional IEEE-754 compliant FPU supporting single- and double-precision operations is also available.

The DesignWare ARC MetaWare Development Toolkit is a complete solution for developing, debugging and optimising embedded software targeted for ARC processors, including the EM DSP processors. It includes an enhanced C/C++ compiler supporting the new DSP instructions for efficient algorithm development. The toolkit also includes a DSP software library of fixed-point math functions and an instruction-accurate simulator that includes accurate modelling of the new DSP operations.

John Koeter, Vice President of Marketing, IP and Prototyping, Synopsys, comments: "There has been a rapid proliferation of feature-rich mobile and IoT electronics needing instantaneous responses to audible commands or movements. Addressing the needs of these low-power designs requires a processor that is highly efficient at processing both control and DSP tasks. The new ARC EM5D and EM7D processors extend the proven EM family with energy-efficient signal processing capabilities ideally suited for the growing number of always-on devices."

ARC EM5D and EM7D processors are scheduled for general availability in July. The associated development tools will be available in June.