Processors deliver up to three times higher DSP performance

The ARC EM9D and EM11D cores deliver the highest level of digital signal processing performance to date in the ARC EM DSP processor family. All EM DSP cores implement a three-stage pipeline and are suitable for applications with a mixture of control and DSP workloads. The EM9D and EM11D take advantage of regular data access patterns common in signal processing code by integrating separate X and Y memories with hardware support for address generation and DMA to move data in and out of the memories. This enables a sustained throughput of one 32x32 MAC operation or two 16x16 MAC operations per clock cycle with minimal energy and area overhead. These new processors have also been enhanced to support full integer, fractional divide and square root operations, unaligned loads/stores and bitstream parsing. These features enable the EM9D and EM11D to deliver the additional DSP performance required to execute complex sensor algorithms, as well as improve processing efficiency for a range of audio formats including MP3, SBC, OPUS and AAC LC. For example, the logic power consumption of the EM9D performing MP3 decode at 44.1kHz, 128kb/s on a 28nm process (nominal) is less than 40mW.

The EM9D and EM11D, like all ARC processor cores, are supported by the DesignWare ARC MetaWare development toolkit, a complete suite of tools for developing, debugging and optimising software targeted for ARC processors. New features to ease DSP programmability and optimise applications for use with the XY memories have been added to the latest MetaWare release. For regular C code, the compiler automatically generates ARCv2DSP ISA instructions to deliver better performance, including guided and auto vectorisation optimisations. Programmers can also efficiently target the cores' DSP and XY memory resources directly through the use of C code with qualifiers and primitives and by making use of the MetaWare Compiler's ability to automatically generate references to XY memory. The MetaWare toolkit includes a rich library of DSP functions such as FFT and DCT, FIR and IIR filters, as well as vector and matrix math functions, allowing software engineers to rapidly implement algorithms from standard DSP building blocks. The toolkit also includes an ITU-T base-ops library for developing voice codecs. For further DSP optimisations, programmers can take advantage of available native fixed-point data types, C++ wrapper classes and an API for fixed-point math primitives. Intrinsics can be used to manually optimise code for maximum performance and power savings.

In addition, the embARC open software platform gives all ARC EM software developers online access to a comprehensive suite of free and open-source software that eases the development of code for IoT and other embedded applications.

"Synopsys' ARC EM9D and EM11D processors are ideally suited for the increasing number of IoT devices using speech comprehension capabilities to enhance hands-free operation," said Dean Neumann, CEO, Malaspina Labs. "The combination of these latest ARC EM cores and highly efficient speech processing software such as Malaspina Labs' VoiceBoost suite delivers an ultra-low power solution for voice activation, biometric verification and speech recognition in 'always listening' devices."

"Today's connected devices draw information from multiple sensors and must respond almost instantly, requiring an increasing amount of processing bandwidth without draining their batteries," commented John Koeter, Vice President of Marketing for IP and Prototyping, Synopsys. "The increased DSP bandwidth of Synopsys' ARC EM9D and EM11D processors gives designers of always-on devices the dual benefits of higher performance for more DSP-intensive tasks and the ability to conserve power by running at lower clock frequencies."