Communications

LDPC NAND FLASH Read Channel For Enterprise Storage

2nd January 2013
ES Admin
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eASIC Corporation and Proton Digital Systems announce the immediate availability of an LDPC NAND FLASH read channel for enterprise storage applications. The combination of IP from Proton Digital Systems and eASIC's NEW ASIC devices enables enterprise storage vendors to double the throughput performance at approximately half the power that can be achieved using state-of–the art FPGAs.
The Proton Digital Systems LDPC read channel enables enterprise FLASH storage system companies to leverage low cost MLC FLASH devices and increase the longevity of the FLASH to 45,000 program/erase cycles, compared to only 5,000 program/erase cycles with traditional BCH algorithms. This essentially extends the operating lifetime of the enterprise storage system to 10 years.

We were keen to work with eASIC as we are increasingly seeing eASIC devices being selected as platforms for enterprise grade customized FLASH controllers, said Dr. Andrei Vityaev, CEO at Proton Digital Systems. In enterprise storage systems, production volumes are often not high enough and the market changes are too dynamic to justify cell-based ASICs but performance and low power requirements are beyond the capability of FPGAs. This makes an eASIC FLASH controller solution ideal for this space. added Dr. Vityaev.

Proton’s FLASH Reliability IP suite is well proven to meet the demands posed by the latest dense NAND FLASH memory geometries, said Jasbinder Bhoot, Vice President of Marketing at eASIC Corporation Robust LDPC-based error correction with soft data collection and signal processing is going to be a must in the enterprise storage space as OEMs strive to increase system endurance while reducing cost by using cheaper NAND FLASH memory. added Bhoot. The eASIC solution is gaining traction in this fast evolving market as the eASIC configurable logic fabric enables fast time to market for a controller optimized for a particular FLASH node. At the same time the power and performance advantages over FPGA make this approach very compelling.

LDPC Read Channel Deliverables

The LDPC Read Channel includes the following deliverables:
-Set of Flash-optimized LDPC codes
-Synthesizable Verilog code with synthesis and simulation scripts
-Integration testbench and tests
-Firmware routines
-Complete reference design system for flash reliability testing with LDPC Read Channel

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