CAN FD passes bit rate tests

The event gathered many of the CiA member companies that are implementing CAN FD in silicon to test the interoperability of their CAN FD implementations using different topologies and transmission speeds. After testing basic functions such as sending and receiving messages, the data phase bit rate was increased in steps from 2Mbit/s to 8Mbit/s. Kvaser’s IP implementation has been designed to support CAN FD bit-rates up to 8Mbit/s with 80MHz clock frequency, so it met the tests with ease.

Kvaser’s Research Manager, Kent Lennartsson conducted the tests on Kvaser’s CAN FD FPGA, as used in Kvaser’s CAN FD compliant interfaces. Talking about the event, he reported: “About 20 different solutions were tested and no major problems were found. Proof of the robustness of CAN FD technology was that the shortening and lengthening of some critical bits didn’t result in faults. This bodes well for the roll-out of CAN FD in the near future.”

A complete set of Kvaser IP modules for CAN FD (Flexible Data Rate) is available to non-strategic customers through Synective Labs. Synective can supply either a bus interfaceable core bundled with demo software, or a BSP (Bit Stream Processor) block, stripped of buffers and other features, making it very small. The IP is available for Xilinx, Altera and other FPGA vendors.