The first article of this two-part series, published in the February 2001 issue of Analog Applications Journal, discussed the THS8083EVM hardware, a TI evaluation module featuring the THS8083 (a triple 8-bit high-speed ADC with integrated PLL for component video and PC graphics digitizing) and the THS8134 (a triple 8-bit video DAC). Having presented an overview of the features and EVM block diagram in the earlier article, we now turn our attention to the design of the complex programmable logic device (CPLD) on the EVM and the design of the PC-user software.
First we will describe the overall functionality of the CPLD, which operates in combination with the THS8083 to enable the display of a digitized PC graphics or video signal on an LCD flat-panel display connected to the board. Then we will focus on the implementation of the communication protocol between the PC and the EVM that eliminates the need for a microcontroller and therefore is more generally applicable as a methodology for rapid hardware prototyping. We will illustrate some of the EVM and THS8083 features using the PC software graphical user interface (GUI); and, in particular, we will implement an algorithm for white-balance calibration.
