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Tensilica - Second Generation ConnX BaseBand Engine DSP for Demanding Algorithms for LTE/4G Wireless Handsets and Base Stations

8th February 2010
ES Admin
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Tensilica introduced ConnX BBE16, its second generation baseband engine for LTE and 4G baseband SOC designs. ConnX BBE16's 16-way MAC architecture is optimized for the most demanding wireless DSP tasks, including OFDM algorithms and FFT, FIR, IIR, and matrix computation.
It is fully optimized for size and power-sensitive applications, and provides up to three times the performance of the original ConnX BBE on some of these critical algorithms. This architecture is particularly suited for system-on-chip designs for programmable radio handsets, low-cost femto-cell and pico-cell base stations, micro and macro base stations, digital media broadcast receivers, and multi-format mobile DTV emodulation.

Tensilica introduced its first ConnX Baseband Engine (BBE) in June of 2009. Tensilica has licensed ConnX BBE to several customers and it is already in volume production. Based on customer feedback, Tensilica developed its next generation DSP: the ConnX BBE16. ConnX BBE16 was developed in record time, leveraging the Tensilica Xtensa® customizable processor foundation technology.

The wireless industry is on a fast track to continuously improve the bandwidth and quality of service to reliably handle the huge increase in wireless data traffic. This requires a constant evolution from 3G to HSPA+, LTE and 4G networks while reducing the overall power budget both in handsets and base stations, stated Jack Guedj, Tensilica's CEO. Designers of next-generation equipment are looking for a more programmable solution so they can quickly evolve their handsets or networks to support the evolving standards. The ConnX BBE16 gives designers a power-efficient, programmable platform which accelerates time to market.

The ConnX BBE16 is an ultra-high performance 16-MAC, 16-bit, fixed-point DSP engine. It is based on an 8-way SIMD (Single Instruction, Multiple Data), 3-way VLIW (Very Long Instruction Word) architecture with two load/store units (each 128b wide).
Enhancements to the ConnX BBE16 DSP include an improved instruction set with added support for:
· Matrix multiplication
· Real and complex FIR filters, including both symmetric and non-symmetric filters
· Polynomial approximations, especially for trigonometric and transcendental functions
· Key wireless functions such as polynomial generation and multiply-accumulate for de-spreading functions (up to 16 complex code MACs/cycle)
· High precision FFTs with adaptive range management
· Expanded support for vector normalization, sifts and packing
· Eight 8x40b accumulator registers (compared to one in the first-generation product) for lower power.

The ConnX BBE16 can achieve 17 GB/s memory bandwidth at 550 MHz. Other performance metrics include: 16 multiply adds per cycle; four complex FIR taps per cycle; and one Radix-4 FFT butterfly per cycle. The improvements results in a 3x speed up on matrix multiplications, up to 3x speed up on FIR filter performance, a 2x improvement in throughput on most common arithmetic functions, and 2

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